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april 2005 1/49 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev. 6 str71xf arm7tdmi ? 16/32-bit mcu with flash, usb, can 5 timers, adc, 10 communications interfaces preliminary data memories ? up to 256+16 kbytes flash memory (100,000 cycles endurance, 20 yrs retention) ? up to 64 kbytes ram ? external memory interface (emi) for up to 4 banks of sram, flash, rom. ? multi-boot capability clock, reset and supply management ? 3.3v application supply and i/o interface ? internal 1.8v voltage regulator for core supply ? 0 to 16 mhz external main oscillator ? 32 khz external backup oscillator ? embedded pll for cpu clock ? up to 50 mhz cpu operating frequency when executing from flash ? realtime clock for clock-calendar function ? 4 power saving modes: slow, wait, stop and standby modes nested interrupt controller ? fast interrupt handling with multiple vectors ? 32 vectors with 16 irq priority levels ? 2 maskable fiq sources up to 48 i/o ports ? 30/32/48 multifunctional bidirectional i/o lines ? 14 ports with inte rrupt capability 5 timers ? 16-bit watchdog timer ? 4 16-bit timers with: 2 input captures, 2 output compares, pwm and pulse counter modes 10 communications interfaces ?2 i 2 c interfaces (1 multiplexed with spi) ? 4 uart asynchronous serial interfaces ? smart card iso7816-3 interface on uart1 ? 2 bspi synchronous serial interfaces ? can interface (2.0b active) ? usb v 2.0 full speed (12mbit/s) device func- tion with suspend and resume support ? hdlc synchronous communications 4-channel 12-bit a/d converter ? conversion time: ? 4 channels: up to 500 hz (2 ms) ? 1 channel: up to 1 khz (1 ms) ? conversion range: 0 to 2.5v development tools support ? jtag with debug mode trigger request table 1. device summary tqfp64 10 x 10 tqfp144 20 x 20 lfbga64 8 x 8 x 1.7 lfbga144 10 x 10 x 1.7 lfbga64 8 x 8 x 1.7 features STR710Fz str711fr str712fr str715fr 12012012 0 flash - kbytes 128+16 256+16 64+16 128+16 256+16 64+16 128+16 256+16 64+16 ram - kbytes 32 64 16 32 64 16 32 64 16 peripheral functions can, emi, usb, 48 i/os usb, 30 i/os can, 32 i/os 32 i/os operating voltage 3.0 to 3.6v (optional 1.8v for core) operating temp. -40 to +85c packages t =tqfp144 20 x 20 h =lfbga144 10 x10 t =tqfp64 10 x10 / h =lfbga64 8 x 8 x 1.7 1 .com .com .com .com 4 .com u datasheet
table of contents 49 2/49 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5 external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.7 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 lvd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 nrstin input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.8 pll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.9 flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.10 external memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.11 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1 note: for detailed information on the str71x f microcontroller memory, registers and peripherals. please refer to the str71xf reference manual. .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 3/49 1 introduction this preliminary data provides the str71x ordering information, mechanical and electrical device characteristics. for complete information on the str71xf micr ocontroller memory, registers and peripherals. please refer to the str71xf reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the str7 flash programming reference manual for information on the arm7tdmi core please refer to the arm7tdmi technical reference manual. 1.1 overview arm ? core with embedded flash & ram the str71xf series is a family of arm-powered 16/32-bit microcontrollers with embedded flash and ram. it combines the high performance arm7tdmi cpu with an extensive range of peripheral functions and enhanced i/o capabilities. all devices have on-chip high-speed single voltage flash memory and high-speed ram. the str71xf family has an embedded arm core and is therefore compatible with all arm tools and software. for information on the arm realview developer kit for st and third-party development tools, please refer to the http://www.st.com website package choice: low pin-count 64-pin or feature-rich 144-pin tqfp or bga the str71xf family is available in 4 main versions. the 144-pin versions have the full set of all features including can, usb and external memory interface. ? STR710F: 144-pin bga or tqfp with can, usb and emi the three 64-pin versions (bga or tqfp) do not include external memory interface. ? str715f: 64-pin bga or tqfp without can or usb ? str711f: 64-pin bga or tqfp with usb ? str712f: 64-pin bga or tqfp with can 1 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 4/49 optional external memory (STR710F ) the non-multiplexed 16-bit data/24-bit address bus available on the STR710F (144-pin) supports four 16-mbyte banks of external memory. wait states are programmable individually for each bank allowing different memory types (flash, eprom, rom, sram etc.) to be used to store programs or data. figure 1 shows the general block diagram of the device family. flexible power management to minimize power consumption, you can program the str71xf to switch to slow, wait for interrupt, stop or standby mode depending on the current system activity in the application. flexible clock control two external clock sources can be used, a main clock and a 32 khz backup clock. the embedded pll allows the internal system clock (up to 50 mhz) to be generated from a main clock frequency of 16 mhz or less. the pll output frequency can be programmed using a wide selection of multipliers and dividers. voltage regulators the str71xf requires an external 3.0-3.6v power supply. there are two internal voltage regulators for generating the 1.8v power supply for the core and peripherals. the main vr is switched off and the low power vr switched on when the application puts the str71xf in standby or low power wait for interrupt (lpwfi) mode. low voltage detectors each voltage regulator has an embedded lvd that monitors the internal 1.8v supply. if the voltage drops below a certain threshold, the lvd will reset the str71xf . on-chip peripherals can interface (STR710F and str712f) the can module is compliant with the can spec ification v2.0 part b (active). the bit rate can be programmed up to 1 mbaud. usb interface (STR710F and str711f) the full-speed usb interface is usb v2.0 compliant and provides up to 8 bidirectional/16 unidirectional endpoints, up to 12 mb/s (ful l-speed), support for bulk transfer and usb suspend/resume functions. 1 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 5/49 standard timers each of the four timers have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a pwm channel with selectable frequency. realtime clock (rtc) the rtc provides a set of continuously running counters driven by a low power 32khz internal oscillator. the rtc can be used as a general timebase or clock/calendar/alarm function. when the str71xf is in standby mode the rtc can be kept running, powered by the low power voltage regulator and driven by the 32khz internal oscillator. uarts the 4 uarts allow full duplex, asynchronous, communications with external devices with independently programmable tx and rx baud rates up to 625 kb/s. smart card interface uart1 is configurable to function either as a general purpose uart or as an asynchronous smart card interface as defined by iso 7816-3. it includes smart card clock generation and provides support features for synchronous cards. buffered serial peripheral interfaces (bspi) each of the two spis allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5mb/s in master mode and 4 mb/s in slave mode. i 2 c interfaces the two i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz) and 7 or 10-bit addressing modes. one i 2 c interface is multiplexed with one spi, so either 2xspi+1x i 2 c or 1xspi+2x i 2 c may be used at a time. hdlc interface the high level data link controller (hdlc) unit supports full duplex operation and nrz, nrzi, fm0 or manchester protocols. it has an internal 8-bit baud rate generator. a/d converter the analog to digital converter, converts in single channel or up to 4 channels in single-shot or continuous conversion modes. resolution is 12-bit with a sample rate of 0.5 khz (1 khz in single channel mode). the input voltage range is 0-2.5v. .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 6/49 watchdog the 16-bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. i/o ports the 48 i/o ports are programmable as inputs or outputs. external interrupts up to 14 external interrupts are available for application use or to wake-up the application from stop mode. .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 7/49 figure 1. str71xf block diagram apb bus usbdp usbdn p0[15:0] i/o port 0 flash memory 64/128/256k i2c0 i2c1 bspi0 bspi1 uart0 uart1 / uart2 uart3 usb can hdlc apb bridge 1 apb bridge 2 apb bus timer1 timer2 timer3 rtc ext int (xti) watchdog interrupt ctl(eic) a/d power supply prccu/pll ram 16/32/64k jtag arm7tdmi cpu ext. mem. stdby 2 af 4 af 4 af 2 af 3 af 2 af 2 af 2 af 3 af 4 af 4 af 2 af 4 af a[19:0] d[15:0] rdn wen[1:0] rtcxto rtcxti wakeup jtdi jtck jtms jtrst jtdo ck ckout rstin v18[1:0] v33[6:0] vss[9:0] v18bkp 14 af osc dbgrqs booten vreg avdd avss p1[15:0] i/o port 1 p2[15:0] i/o port 2 timer0 arm7 native bus cs[3:0) 2 af 1 af af: alternate function on i/o port pin interface (emi) a[23:20] smart card 16k rww flash .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 8/49 1.2 related documentation available from www.arm.com: arm7tdmi technical reference manual available from http://www.st.com: str71x reference manual str7 flash programming reference manual an1774 - getting started with str71xf software development an1775 - getting started with str71xf hardware development an1776 - str71xf enhanced interrupt controller an1777 - str71xf memory mapping an1778 - str71xf multi-ice setup an1780 - real time clock with str71xf an1781 - four 7 segment display drive using the str71xf the above is a selected list only, a full li st str71x application notes can be viewed at http://www.st.com . .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 9/49 1.3 pin description for 144-pin packages figure 2. str710 tqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p0.10/u1.rx/u1.tx/scdata rdn p0.11/u1.tx/boot.1 p0.12/scclk vss v33 p2.0/csn.0 p2.1/csn.1 p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa p2.2/csn.2 p2.3/csn.3 p2.4/a.20 p2.5/a.21 p2.6/a.22 booten p2.7/a.23 p2.8 n.c. n.c. vss v33 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 jtdi jtms jtck jtdo jtrstn nu test p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 v33 vss a.4 a.3 a.2 a.1 a.0 d.15 d.14 d.13 d.12 d.11 d.10 usbdn usbdp p1.12/cantx p1.11/canrx n.c. p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll d.9 d.8 d.7 d.6 d.5 p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 n.c. test n.c. v33io-pll n.c. vssio-pll n.c. dbgrqs ckout ck p0.15/wakeup n.c. rtcxti rtcxto stdbyn rstinn n.c. vssbkp v18bkp n.c. n.c. v18 vss18 n.c. d.0 d.1 d.2 d.3 d.4 avdd avss n.c. n.c. n.c. p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v33 wen.0 wen.1 a.19 a.18 a.17 a.16 a.15 a.14 v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx a.13 a.12 a.11 a.10 a.9 a.8 a.7 a.6 a.5 v33 vss p1.15/htxd n.c. n.c. tqfp144 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 10/49 table 2. str710 bga ball connections abcdefghjklm 1 p0.10 p2.0 p2.1 vss p2.2 p2.6 boot en p2.12 p2.13 p2.15 jtdi n.c. 2 vss rdn p0.11 v33 p2.3 p2.8 p2.9 jtms jtrstn test test n.c. 3 v33 p0.9 p0.12 p0.13 p2.4 vss p2.10 jtck nu v33 n.c. dbg rqs 4 p0.6 p0.7 p0.8 p0.14 p2.5 n.c. p2.11 jtdo ck ckout vssio- pll n.c. 5 a.19 wen.1 wen.0 p0.5 p2.7 n.c. p2.14 nc rtcx- to rtcxti nc p0.15 6 p0.3 a.15 a.16 a.17 a.18 v33 v18 n.c. n.c. v18bkp vss bkp stdbyn 7 p0.2 p0.1 p0.4 vss18 v18 a.14 d.12 d.1 d.0 nc vss18 rstinn 8 a.9 a.10a.11a.13p0.0 a.0 d.11 p1.12/ cantx n.c. avss d.3 d.2 9 vss v33 a.5 a.6 v33 d.15 d.10 p1.8 d.9 p1.0 n.c. n.c. 10 a.8 n.c. p1.15 p1.13 vss d.14 usbdn p1.7 d.8 p1.5 p1.1 d.4 11 a.7 n.c. p1.14 p1.10 a.2 d.13 usbdp vss d.5 p1.4 p1.3 avdd 12 a.12 a.4 a.3 p1.9 a.1 n.c. p1.11/ canrx v33io- pll p1.6 d.7 d.6 p1.2 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 11/49 legend / abbreviations for table 3 : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.8v / 2v with input trigger t t = ttl 0.3v dd /0.7v dd with input trigger c/t = programmable levels: cmos 0.3v dd /0.7v dd or ttl 0.8v / 2v port and control configuration: ? input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k ? weak pull-up is enabled. pd = in reset state, the internal 100k ? weak pull-down is enabled. ? output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and protection diode to v dd not implemented), 5v tolerant. table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp 1a1 p0.10/u1.rx/ u1.tx/ sc.data i/o pd c t x4ma t port 0.10 uart1: receive data input uart1: transmit data output. note: this pin may be used for smartcard datain/dataout or single wire uart (half du- plex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 2b2rd ox external memory interface: active low read signal for external memory. it maps to the oe_n input of the ex- ternal components. 3c2 p0.11/ boot.1/ u1.tx i/o pd c t 4ma x x port 0.11 select boot con- figuration input uart1: transmit data output. 4 c3 p0.12/sc.clk i/o pd c t 4ma port 0.12 smartcard reference clock output 5d1v ss s ground voltage for digital i/os 6d2v 33 s supply voltage for digital i/os 7 b1 p2.0/cs .0 i/o pu c t 8ma x x port 2.0 external memory interface: select memory bank 0 output note: this pin is forced to output mode at re- set to allow boot from external memory 8 c1 p2.1/cs .1 i/o pu 2) c t 8ma x x port 2.1 external memory interface: select memory bank 1 output 9d3 p0.13/u2.rx/ t2.ocmpa i/o pu c t x4ma x x port 0.13 uart2: receive data input timer2: output compare a output 10 d4 p0.14/u2.tx/ t2.icapa i/o pu c t 4ma x x port 0.14 uart2: transmit data output timer2: input capture a input 11 e1 p2.2/cs .2 i/o pu 2) c t 8ma x x port 2.2 external memory interface: select memory bank 3 output .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 12/49 12 e2 p2.3/cs .3 i/o pu 2) c t 8ma x x port 2.3 external memory interface: select memory bank 4 output 13 e3 p2.4/a.20 i/o pd 3) c t 8ma x x port 2.4 external memory interface: address bus 14 e4 p2.5/a.21 i/o pd 3) c t 8ma x x port 2.5 15 f1 p2.6/a.22 i/o pd 3) c t 8ma x x port 2.6 16 g1 booten i c t boot control input. enables sampling of boot[1:0] pins 17 e5 p2.7/a.23 i/o pd 3) c t 8ma x x port 2.7 external memory interface: address bus 18 f2 p2.8 i/o pu c t x 4ma x x port 2.8 external interrupt int2 19 f4 n.c. not connected (not bonded) 20 f5 n.c. not connected (not bonded) 21 f3 v ss s ground voltage for digital i/os 22 f6 v 33 s supply voltage for digital i/os 23 g2 p2.9 i/o pu c t x 4ma x x port 2.9 external interrupt int3 24 g3 p2.10 i/o pu c t x4ma x x port 2.10 external interrupt int4 25 g4 p2.11 i/o pu c t x4ma x x port 2.11 external interrupt int5 26 h1 p2.12 i/o pu c t 4ma x x port 2.12 27 j1 p2.13 i/o pu c t 4ma x x port 2.13 28 g5 p2.14 i/o pu c t 4ma x x port 2.14 29 k1 p2.15 i/o pu c t 4ma x x port 2.15 30 l1 jtdi i t t jtag data input. external pull-up required. 31 h2 jtms i t t jtag mode selection input. external pull-up required. 32 h3 jtck i c jtag clock input. external pull-up or pull-down re- quired. 33 h4 jtdo o 8ma x jtag data output. note: reset state = hiz. 34 j2 jtrst it t jtag reset input. external pull-up required. 35 j3 nu reserved, must be forced to ground. 36 k2 test reserved, must be forced to ground. 37 l3 n.c. not connected (not bonded) 38 l2 test reserved, must be forced to ground. 39 m1 n.c. not connected (not bonded) table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 13/49 40 k3 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 41 m2 n.c. not connected (not bonded) 42 l4 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 43 m4 n.c. not connected (not bonded) 44 m3 dbgrqs i c t debug mode request input (active high) 45 k4 ckout o 8ma x clock output (f pclk2 ) note: enabled by ckdis register in apb bridge 2 46 j4 ck i c reference clock input 47 m5 p0.15/wake- up iput t x4ma x port 0.15 wakeup from standby mode input. 48 l5 n.c. not connected (not bonded) 49 k5 rtcxti realtime clock input and input of 32 khz oscillator am- plifier circuit 50 j5 rtcxto output of 32 khz oscillator amplifier circuit 51 m6 stdby i/o c t 4ma x x input: hardware standby mode entry input active low. caution: external pull-up to v 33 required to select nor- mal mode. output: standby mode active low output following soft- ware standby mode entry. note : in standby mode all pins are in high impedance except those marked active in stdby 52 m7 rstin ic t x reset input 53 j6 n.c. not connected (not bonded) 54 l6 v ssbkp s x stabilisation for low power voltage regulator. 55 k6 v 18bkp sx stabilisation for low power voltage regulator. requires external capacitors of at least 1f between v 18bkp and v ss18bkp . see figure 5 . note: if the low power voltage regulator is bypassed, this pin can be connected to an external 1.8v supply. 56 h5 n.c. not connected (not bonded) 57 h6 n.c. not connected (not bonded) 58 g6 v 18 s stabilisation for main volt age regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 59 l7 v ss18 s stabilisation for ma in voltage regulator. 60 k7 n.c. not connected (not bonded) table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 14/49 61 j7 d.0 i/o 8ma external memory interface: data bus 62 h7 d.1 i/o 8ma 63 m8 d.2 i/o 8ma 64 l8 d.3 i/o 8ma 65 m10 d.4 i/o 8ma 66 m11 v dda s supply voltage for a/d converter 67 k8 v ssa s ground voltage for a/d converter 68 j8 n.c. not connected (not bonded) 69 l9 n.c. not connected (not bonded) 70 m9 n.c. not connected (not bonded) 71 k9 p1.0/t3.oc- mpb/ain.0 i/o pu c t 4ma x x port 1.0 timer 3: output compare b adc: analog input 0 72 l10 p1.1/t3.ica- pa/t3.ext- clk/ain.1 i/o pu c t 4ma x x port 1.1 timer 3: input capture a or ex- ternal clock input adc: analog input 1 73 m12 p1.2/t3.ocm- pa/ain.2 i/o pu c t 4ma x x port 1.2 timer 3: output compare a adc: analog input 2 74 l11 p1.3/ t3.icapb/ ain.3 i/o pu c t 4ma x x port 1.3 timer 3: input capture b adc: analog input 3 75 k11 p1.4/t1.ica- pa/t1.ext- clk i/o pu c t 4ma x x port 1.4 timer 1: input capture a timer 1: external clock input 76 k10 p1.5/ t1.icapb i/o pu c t 4ma x x port 1.5 timer 1: input capture b 77 j12 p1.6/t1.oc- mpb i/o pu c t 4ma x x port 1.6 timer 1: output compare b 78 j11 d.5 i/o 8ma external memory interface: data bus 79 l12 d.6 i/o 8ma 80 k12 d.7 i/o 8ma 81 j10 d.8 i/o 8ma 82 j9 d.9 i/o 8ma 83 h12 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 84 h11 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 85 h10 p1.7/t1.ocm- pa i/o pu c t 4ma x x port 1.7 timer 1: output compare a 86 h9 p1.8 i/o pd c t 4ma x x port 1.8 87 f12 n.c. not connected (not bonded) table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 15/49 88 g12 p1.11/canrx i/o pu c t x4ma x x port 1.11 can: receive data input note: on str710 and str712 only 89 h8 p1.12/cantx i/o pu c t x4ma x x port 1.12 can: transmit data output note: on str710 and str712 only 90 g11 usbdp i/o c t usb bidirectional data (dat a +). reset state = hiz note: on str710 and str711 only this pin requires an external pull-up to v 33 to maintain a high level. 91 g10 usbdn i/o c t usb bidirectional data (dat a -). reset state = hiz note: on str710 and str711 only. 92 g9 d.10 i/o 8ma external memory interface: data bus 93 g8 d.11 i/o 8ma 94 g7 d.12 i/o 8ma 95 f11 d.13 i/o 8ma 96 f10 d.14 i/o 8ma 97 f9 d.15 i/o 8ma 98 f8 a.0 o 8ma external memory interface: address bus 99 e12 a.1 o 8ma 100 e11 a.2 o 8ma 101 c12 a.3 o 8ma 102 b12 a.4 o 8ma 103 e10 v ss s ground voltage for digital i/o circuitry 104 e9 v 33 s supply voltage for digital i/o circuitry 105 d12 p1.9 i/o pd c t 4ma x x port 1.9 106 d11 p1.10/usb- clk i/o pu c/t 4ma x x port 1.10 usb: 48 mhz clock input 107 d10 p1.13/hclk/ i0.scl i/o pu c t x4ma x x port 1.13 hdlc: reference clock input i2c clock 108 c11 p1.14/hrxd/ i0.sda i/o pu c t x4ma x x port 1.14 hdlc: receive data input i2c serial data 109 b11 n.c. not connected (not bonded) 110 b10 n.c. not connected (not bonded) 111 c10 p1.15/htxd i/o pu c t x4ma x x port 1.15 hdlc: transmit data output 112 a9 v ss s ground voltage for digital i/o circuitry 113 b9 v 33 s supply voltage for digital i/o circuitry table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 16/49 114 c9 a.5 o 8ma external memory interface: address bus 115 d9 a.6 o 8ma 116 a11 a.7 o 8ma 117 a10 a.8 o 8ma 118 a8 a.9 o 8ma 119 b8 a.10 o 8ma 120 c8 a.11 o 8ma 121 a12 a.12 o 8ma 122 d8 a.13 o 8ma 123 e8 p0.0/s0.miso/ u3.tx i/o pu c t 4ma x x port 0.0 spi0 master in/ slave out data uart3 transmit data output note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 124 b7 p0.1/s0.mosi/ u3.rx i/o pu c t x4ma x x port 0.1 bspi0: master out/slave in data uart3: receive data in- put note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 125 a7 p0.2/ s0.sclk/ i1.scl i/o pu c t x4ma x x port 0.2 bspi0: serial clock i2c1: serial clock note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 126 a6 p0.3/s0.ss / i1.sda i/o pu c t 4ma x x port 0.3 spi0: slave se- lect input active low. i2c1: serial data note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 127 c7 p0.4/s1.miso i/o pu c t 4ma x x port 0.4 spi1: master in/slave out data 128 d7 v ss18 s stabilisation for ma in voltage regulator. 129 e7 v 18 s stabilisation for main volt age regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 130 f7 a.14 o 8ma external memory interface: address bus 131 b6 a.15 o 8ma 132 c6 a.16 o 8ma 133 d6 a.17 o 8ma 134 e6 a.18 o 8ma 135 a5 a.19 o 8ma table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 17/49 1. the reset configuration of the i/o ports is ipupd (input pull-up/pull down). refer to table 7, ?port bit configuration table,? on page 26 . the port bit configuration at reset is pc0=1, pc1=1, pc2=0. the port data register bit (pd) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. in reset state, these pins configured as input pu/pd with weak pull-up enabled. they must be configured by software as alternate function (see table 7, ?port bit configuration table,? on page 26 ) to be used by the external memory interface. 3. in reset state, these pins configured as inpu t pu/pd with weak pull-down enabled to output address 0x0000 0000 using the external memory interface. to access memory banks greater than 1mbyte, they need to be configured by software as alternate function (see table 7, ?port bit configuration table,? on page 26 ). 136 b5 we .1 o 8ma external memory interface: active low msb write ena- ble output 137 c5 we .0 o 8ma external memory interface: active low lsb write enable output 138 a3 v 33 s supply voltage for digital i/os 139 a2 v ss s ground voltage for digital i/os 140 d5 p0.5/s1.mosi i/o pu c t 4ma x x port 0.5 spi1: mast er out/slave in data 141 a4 p0.6/s1.sclk i/o pu c t x 4ma x x port 0.6 spi1: serial clock 142 b4 p0.7/s1.ss i/o pu c t 4ma x x port 0.7 spi1: slave select input active low 143 c4 p0.8/u0.rx/ u0.tx i/o pd c t x4ma t port 0.8 uart0: receive data input uart0: transmit data output. note: this pin may be used for single wire uart (half duplex) if programmed as al ternate function output. the pin will be tri-stated except when uart transmis- sion is in progress 144 b3 p0.9/u0.tx/ boot.0 i/o pd c t 4ma x x port 0.9 select boot con- figuration input uart0: transmit data output table 3. str710 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp144 bga144 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 18/49 1.4 pin description for 64-pin packages figure 3. str712f/str715f tqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10 p1.9 vss p1.12/cantx 1) p1.11/canrx 1) p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto nstdby nrstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd tqfp64 1) cantx and canrx in str712f only, in str715f they are general purpose i/os. .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 19/49 figure 4. str711f tqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 vss usbdn usbdp p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto nstdby nrstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd tqfp64 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 20/49 table 4. str711f bga ball connections table 5. str712f/715f bga ball connections 1) cantx and canrx in str712f only, in st r715f they are general purpose i/os. abcdefgh 1 p0.10 p0.11 p0.12 p0.14 v33 jtck test v33io-pll 2 p0.9 vss p0.13 vss jtms jtrstn p0.15 vssio-pll 3 p0.5 p0.7 booten jtdi nu stdbyn rtcxti ck 4 vss18 vss p0.8 jtdo avdd v18bkp rstinn rtcxto 5 p0.2 p0.4 v18 p0.6 p1.9 p1.0 v18 vssbkp 6 v33 p0.1 p0.3 p1.13 usbdp vssio-pll avss vss18 7 vss p0.0 p1.10 usbdn p1.7 p1.6 p1.5 p1.1 8 p1.15 p1.14 vss p1.8 v33io-pll p1.4 p1.3 p1.2 abcdefgh 1 p0.10 p0.11 p0.12 p0.14 v33 jtck test v33io-pll 2 p0.9 vss p0.13 vss jtms jtrstn p0.15 vssio-pll 3 p0.5 p0.7 booten jtdi nu stdbyn rtcxti ck 4 vss18 vss p0.8 jtdo avdd v18bkp rstinn rtcxto 5 p0.2 p0.4 v18 p0.6 p1.9 p1.0 v18 vssbkp 6 v33 p0.1 p0.3 p1.13 p1.11/ canrx 1) vssio-pll avss vss18 7 vss p0.0 p1.10 p1.12/ cantx 1) p1.7 p1.6 p1.5 p1.1 8 p1.15 p1.14 vss p1.8 v33io-pll p1.4 p1.3 p1.2 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 21/49 legend / abbreviations for table 3 : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.8v / 2v with input trigger t t = ttl 0.3v dd /0.7v dd with input trigger c/t = programmable levels: cmos 0.3v dd /0.7v dd or ttl 0.8v / 2v port and control configuration: ? input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k ? weak pull-up is enabled. pd = in reset state, the internal 100k ? weak pull-down is enabled. ? output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and protection diode to v dd not implemented), 5v tolerant. table 6. str711/str712/str715 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp64 bga64 input level interrupt capability od pp 1a1 p0.10/u1.rx/ u1.tx/ sc.data i/o pd c t x4ma t port 0.10 uart1: receive data input uart1: transmit data output. note: this pin may be used for smartcard datain/dataout or singl e wire uart (half du- plex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 2b1 p0.11/ boot.1/ u1.tx i/o pd c t 4ma x x port 0.11 select boot con- figuration input uart1: transmit data output. 3 c1 p0.12/sc.clk i/o pd c t 4ma port 0.12 smartcard reference clock output 4b2v ss s ground voltage for digital i/os 5c2 p0.13/u2.rx/ t2.ocmpa i/o pu c t x4ma x x port 0.13 uart2: receive data input timer2: output compare a output 6d1 p0.14/u2.tx/ t2.icapa i/o pu c t 4ma x x port 0.14 uart2: transmit data output timer2: input capture a input 7 c3 booten i c t boot control input. enables sampling of boot[1:0] pins 8d2v ss s ground voltage for digital i/os 9e1v 33 s supply voltage for digital i/os 10 d3 jtdi i t t jtag data input. external pull-up required. 11 e2 jtms i t t jtag mode selection input. external pull-up required. 12 f1 jtck i c jtag clock input. external pull-up or pull-down re- quired. 13 d4 jtdo o 8ma x jtag data output. note: reset state = hiz. 14 f2 jtrst it t jtag reset input. exte rnal pull-up required. 15 e3 nu reserved, must be forced to ground. .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 22/49 16 g1 test reserved, must be forced to ground. 17 h1 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 18 h2 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 19 h3 ck i c reference clock input 20 g2 p0.15/wake- up iput t x4ma x port 0.15 wakeup from standby mode input. 21 g3 rtcxti realtime clock input and input of 32 khz oscillator am- plifier circuit 22 h4 rtcxto output of 32 khz o scillator amplifier circuit 23 f3 stdby i/o c t 4ma x x input: hardware standby mode entry input active low. caution: external pull-up to v 33 required to select nor- mal mode. output: standby mode active low output following soft- ware standby mode entry. note : in standby mode all pins are in high impedance except those marked active in stdby 24 g4 rstin ic t x reset input 25 h5 v ssbkp s x stabilisation for low power voltage regulator. 26 f4 v 18bkp sx stabilisation for low power voltage regulator. requires external capacitors of at least 1f between v 18bkp and v ss18bkp . see figure 5 . note: if the low power voltage regulator is bypassed, this pin can be connected to an external 1.8v supply. 27 g5 v 18 s stabilisation for main voltage regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 28 h6 v ss18 s stabilisation for main voltage regulator. 29 e4 v dda s supply voltage for a/d converter 30 g6 v ssa s ground voltage for a/d converter 31 f5 p1.0/t3.oc- mpb/ain.0 i/o pu c t 4ma x x port 1.0 timer 3: output compare b adc: analog input 0 32 h7 p1.1/t3.ica- pa/t3.ext- clk/ain.1 i/o pu c t 4ma x x port 1.1 timer 3: input capture a or ex- ternal clock input adc: analog input 1 33 h8 p1.2/t3.ocm- pa/ain.2 i/o pu c t 4ma x x port 1.2 timer 3: output compare a adc: analog input 2 34 g8 p1.3/ t3.icapb/ ain.3 i/o pu c t 4ma x x port 1.3 timer 3: input capture b adc: analog input 3 table 6. str711/str712/str715 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp64 bga64 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 23/49 35 f8 p1.4/t1.ica- pa/t1.ext- clk i/o pu c t 4ma x x port 1.4 timer 1: input capture a timer 1: external clock input 36 g7 p1.5/ t1.icapb i/o pu c t 4ma x x port 1.5 timer 1: input capture b 37 f7 p1.6/t1.oc- mpb i/o pu c t 4ma x x port 1.6 timer 1: output compare b 38 e8 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 39 f6 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 40 e7 p1.7/t1.ocm- pa i/o pu c t 4ma x x port 1.7 timer 1: output compare a 41 d8 p1.8 i/o pd c t 4ma x x port 1.8 42 e6 p1.11/canrx i/o pu c t x4ma x x port 1.11 can: receive data input note: on str710 and str712 only 43 d7 p1.12/cantx i/o pu c t x4ma x x port 1.12 can: transmit data output note: on str710 and str712 only 42 e6 usbdp i/o c t usb bidirectional data (dat a +). reset state = hiz note: on str710 and str711 only this pin requires an external pull-up to v 33 to maintain a high level. 43 d7 usbdn i/o c t usb bidirectional data (dat a -). reset state = hiz note: on str710 and str711 only. 44 c8 v ss s ground voltage for digital i/o circuitry 45 e5 p1.9 i/o pd c t 4ma x x port 1.9 46 c7 p1.10/usb- clk i/o pu c/t 4ma x x port 1.10 usb: 48 mhz clock input 47 d6 p1.13/hclk/ i0.scl i/o pu c t x4ma x x port 1.13 hdlc: reference clock input i2c clock 48 b8 p1.14/hrxd/ i0.sda i/o pu c t x4ma x x port 1.14 hdlc: receive data input i2c serial data 49 a8 p1.15/htxd i/o pu c t x4ma x x port 1.15 hdlc: transmit data output 50 a7 v ss s ground voltage for digital i/o circuitry 51 a6 v 33 s supply voltage for digital i/o circuitry 52 b7 p0.0/s0.miso/ u3.tx i/o pu c t 4ma x x port 0.0 spi0 master in/ slave out data uart3 transmit data output note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. table 6. str711/str712/str715 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp64 bga64 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 24/49 1. the reset configuration of the i/o ports is ipupd (input pull-up/pull down). refer to table 7, ?port bit configuration table,? on page 26 . the port bit configuration at reset is pc0=1, pc1=1, pc2=0. the port data register bit (pd) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. in reset state, these pins configured as input pu/pd with weak pull-up enabled. they must be configured by software as alternate function (see table 7, ?port bit configuration table,? on page 26 ) to be used by the external memory interface. 53 b6 p0.1/s0.mosi/ u3.rx i/o pu c t x4ma x x port 0.1 bspi0: master out/slave in data uart3: receive data in- put note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 54 a5 p0.2/ s0.sclk/ i1.scl i/o pu c t x4ma x x port 0.2 bspi0: serial clock i2c1: serial clock note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 55 c6 p0.3/s0.ss / i1.sda i/o pu c t 4ma x x port 0.3 spi0: slave se- lect input active low. i2c1: serial data note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 56 b5 p0.4/s1.miso i/o pu c t 4ma x x port 0.4 spi1: mast er in/slave out data 57 a4 v ss18 s stabilisation for main voltage regulator. 58 c5 v 18 s stabilisation for main voltage regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 59 b4 v ss s ground voltage for digital i/os 60 a3 p0.5/s1.mosi i/o pu c t 4ma x x port 0.5 spi1: master out/slave in data 61 d5 p0.6/s1.sclk i/o pu c t x 4ma x x port 0.6 spi1: serial clock 62 b3 p0.7/s1.ss i/o pu c t 4ma x x port 0.7 spi1: slave select input active low 63 c4 p0.8/u0.rx/ u0.tx i/o pd c t x4ma t port 0.8 uart0: receive data input uart0: transmit data output. note: this pin may be used for single wire uart (half duplex) if programmed as al ternate function output. the pin will be tri-stated e xcept when uart transmis- sion is in progress 64 a2 p0.9/u0.tx/ boot.0 i/o pd c t 4ma x x port 0.9 select boot con- figuration input uart0: transmit data output table 6. str711/str712/str715 pin description pin n pin name type input reset state 1) input output active in stdby main function (after reset) alternate function tqfp64 bga64 input level interrupt capability od pp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 25/49 3. in reset state, these pins configured as inpu t pu/pd with weak pull-down enabled to output address 0x0000 0000 using the external memory interface. to access memory banks greater than 1mbyte, they need to be configured by software as alternate function (see table 7, ?port bit configuration table,? on page 26 ). .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 26/49 1.5 external connections figure 5. recommended external connection of v 18 and v 18bkp pins 1.6 i/o port configuration table 7. port bit configuration table port configuration registers (bit) values pc0(n) 01010101 pc1(n) 00110011 pc2(n) 00001111 configuration hiz/ain in in ipupd out out af af output tri tri tri wp od pp od pp input ain ttl cmos cmos n.a. n.a. cmos cmos notes: af: alternate function od: open drain ain: analog input out: output ipupd: input pull up /pull down pp: push-pull cmos: cmos input levels tri: tristate hiz: high impedance ttl: ttl input levels in: input wp: weak push-pull n.a. not applicable. in output mode, a read access to the port gets the output latch value). tqfp144 tqfp64 58 57 27 129 128 33 nf 59 10 f 10 f 33 nf 54 55 1f 25 26 1f 28 58 v 18bkp v 18 v 18 v 18 v 18 v 18bkp .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 27/49 1.7 memory mapping figure 6. memory map apb bridge 2 regs addressable memory space 0 1 2 3 4 4k 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0xc000 0000 0xc000 1000 0xc000 2000 0xc000 3000 0xc000 4000 0xc000 5000 0xc000 6000 0xc000 7000 0xc000 8000 0xc000 9000 0xc000 a000 0xc000 b000 0xc000 c000 0xe000 1000 0xe000 2000 0xe000 3000 0xe000 4000 0xffff ffff 0x0000 0000 apb memory space 4 gbytes flash/ram/emi extmem 1k 0xffff f800 4k eic 0xffff f800 apb bridge 1 regs reserved flash 256k+16k+32b b0f0 b0f4 b0f5 b0f6 b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 272 kbytes + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 4k (*) flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon reset from block b0 (8 kbytes) 0xe000 0000 0xe000 5000 0xe000 6000 0xe000 7000 0xe000 8000 0xe000 9000 0xe000 a000 0xe000 b000 i 2 c 0 i2c 1 reserved uart 0 uart 1 uart 2 uart 3 usb + ram bspi 0 bspi 1 xti reserved ioport 1 ioport 2 adc clkout timer 3 rtc wdg 0xe000 e000 0xe000 d000 0xe000 c000 0xc000 d000 0xc000 e000 prccu 1k can b0f7 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k timer 0 timer 1 timer 2 reserved reserved hdlc + ram reserved 0xc001 0000 0xc000 f000 b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 20b flash registers 0x4000 2000 ram 64k apb1 apb2 eic b0f2 b0f1 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k reserved reserved ioport 0 64k 64k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k b0f3 8k 8k 0x4000 8000 .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 28/49 figure 7. mapping of flash memory versions table 8. ram memory mapping part number ram size start address end address str715fr0xx str711fr0xx str712fr0xx 16 kbytes 0x2000 0000 0x2000 3fff STR710Fz1xx str711fr1xx str712fr1xx 32 kbytes 0x2000 0000 0x2000 7fff STR710F72xx str711fr2xx str712fr2xx 64 kbytes 0x2000 0000 0x2000 ffff b0f0 b0f4 reserved reserved b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 64 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 20b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 b0f0 b0f4 b0f5 reserved b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 128 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 20b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 b0f0 b0f4 b0f5 b0f6 b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 256 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 b0f7 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 20b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 str715fr0xx str711fr0xx str712fr0xx str711fr1xx str712fr1xx STR710F72xx str711fr2xx str712fr2xx STR710Fz1xx .com .com .com .com .com 4 .com u datasheet
str71xf - introduction 29/49 figure 8. external memory map drawing not in scale addressable memory space 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 4 gbytes flash/ram/emi extmem 0xffff f800 reserved flash bcon3 bank3 bank2 0x6000 0000 16m 16m 16m 16m 0x6200 0000 0x6400 0000 0x6600 0000 reserved prccu bank1 ram apb1 apb2 eic bcon1 bcon2 bcon0 0x6c00 0000 0x6c00 0004 0x6c00 0008 0x6c00 000c register register register register bank0 external memory space 64 mbytes csn.0 csn.1 csn.2 csn.3 0x60ff ffff 0x62ff ffff 0x64ff ffff 0x66ff ffff .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 30/49 2 electrical characteristics 2.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation, it is recommended that v in and v o be higher than v ss and lower than v 33 . reliability is enhanced if unused input s are connected to an appropriate logic voltage level (v 33 or v ss ). table 9. absolute maximum ratings. note stresses exceeding above listed recommended ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v 33 or v in str71xf - electrical characteristics 31/49 2.2 operating conditions note ram data retention is guaranteed with v 33 not below 2.7 volt, with the device in low power mode (stop or wait for interrupt). 2.3 lvd electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 10. lvd electrical characteristics symbol parameter value unit min max v 33 digital supply voltage fo r i/o circuitry 3.0 3.6 v v 33io-pll digital supply voltage for i/o circ uitry and for pll reference 3.0 3.6 v v 18bkp external supply voltage for backup bl ock (voltage regulat or off) 1.4 1.8 v av dd analog supply voltage for the a/d converter v 33 v 33 v t a ambient temperature under bias ?40 +85 c t j junction temperature under bias ?40 +105 c symbol parameter test conditions value unit min typ max v it lvd threshold main and lp lvds 1.3 1.45 v .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 32/49 2.4 dc electrical characteristics v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. table 11. dc electrical characteristics symbol parameter comment value unit min typ max v ih input high level cmos with or w/o hysteresis 0.7v 33 v input high level p0.15 (wakeup) only 1.8 v v il input low level cmos with or w/o hysteresis 0.3v 33 v input low level p0.15 (wakeup) only 0.7 v v hys input hysteresis cmos schmitt trigger 0.4 0.8 1.2 v input hysteresis schmitt trigger p0.15 (wakeup) only 0.3 0.5 v v oh output high level high current pins push pull, i oh = 8ma v 33 ? 0.8 v output high level standard current pins push pull, i oh = 4ma v 33 ? 0.8 v v ol output low level high current pins push pull, i ol = 8ma 0.4 v output low level standard current pins push pull, i ol = 4ma 0.4 v r wpu weak pull-up resistor measured at 0.5v 33 100 k ? r wpd weak pull-down resi stor measured at 0.5v 33 100 k ? .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 33/49 2.5 ac electrical characteristics v 33 = 3.3v 10%, t a = 27 c unless otherwise specified. note i ddrun is the power consumption in applications exploiting the full performances of the core (running at the maximum frequency). note i ddwfi is the power consumption with plls off, vreg and flash on. this guarantees the minimum interrupt response time. note i ddlp is the power consumption with plls, main vreg and flash off. 1) refer to apbn_ckdis register description. table 12. power consumption symbol parameter conditions value unit min typ max i ddrun run mode current mclk=50 mhz see table 13 100 ma i ddwfi wfi mode current 1 mhz system clock 3 6 ma i ddlp lpwfi mode current 32 khz system clock 200 a i ddstp stop mode current main vreg of f, flash in power-down 100 a i ddsb1 standby mode current lp vreg and 32khz osc on 15 30 a i ddsb0 standby mode current lp vreg, lvd, 32khz osc bypassed 3 10 a table 13. i ddrun typical data measurements, t a =25c frequency all peripheral clocks enabled 1) (reset configuration) all peripheral clocks disabled 1) unit ram execution flash execution ram execution flash execution mclk=1 mhz pclk=1 mhz 15 15 11 11 ma mclk=8 mhz pclk=8 mhz 19 20 15 17 mclk=16 mhz pclk=8 mhz 23 27 19 23 mclk=48 mhz pclk=6 mhz 43 53 40 50 mclk=64 mhz pclk=8 mhz 53 n/a 48 n/a .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 34/49 v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. 2.6 nrstin input filter characteristics v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. table 15. nrstin input filter characteristics table 14. ac electrical characteristics symbol parameter conditions value unit min typ max f mclk cpu frequency executing from ram or external memory 66 mhz executing from flash 50 executing from flash with rww 45 burst mode disabled (flashlp bit =1) 33 f pclk peripheral clock for apb 33 f ck clock input pin 16 symbol parameter conditions value unit min typ max t fr nrstin input filtered pulse 500 ns t nfr nrstin input not filtered pulse 1.2 s .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 35/49 2.7 oscillator electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. figure 9. crystal oscillator and resonator table 16. oscillator electrical characteristics 2.8 pll electrical characteristics v 33 = 3.3 10%, v 33iopll = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 17. pll1 electrical characteristics symbol parameter test conditions value unit min typ max g m oscillator transconductance 8 a/v t stup oscillator start-up time stable v 33 2.5 s symbol parameter test conditions value unit min typ max f pllclk1 pll output clock f pll1 x 24 165 mhz f pll1 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 mx[1:0]=?00? or ?01? 3.0 8.25 mhz fref_range = 1 mx[1:0]=?10? or ?11? 3.0 6 mhz pll input clock duty cycle 25 75 % c l c l rtcxti rtcxto r s rtcxti rtcxto device device .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 36/49 table 18. pll2 electrical characteristics f free1 pll free running frequency fref_range = 0 mx[1:0]=?01? or ?11? 1mhz fref_range = 0 mx[1:0]=?00? or ?10? 2mhz fref_range = 1 mx[1:0]=?01? or ?11? 2mhz fref_range = 1 mx[1:0]=?00? or ?10? 4mhz t lock1 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter1 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns symbol parameter test conditions value unit min typ max f pllclk2 pll output clock f pll x 28 140 mhz f pll2 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 3.0 5 mhz t lock2 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter2 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns symbol parameter test conditions value unit min typ max .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 37/49 2.9 flash electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 19. flash program/erase characteristics 1 note c 0 : t a = 85 c after 0 cycles c max : t a = 85 c after max number of cycles table 20. flash program/erase characteristics 2 symbol parameter test conditions value unit typ max(c 0 ) max(c max ) t pw word program 40 s t pdw double word program 60 s t pb0 bank 0 program (256k) double word program 1.6 2.1 4.3 s t pb1 bank 1 program (16k) double word program 130 170 300 ms t es sector erase (64k) not preprogrammed preprogrammed 2.3 1.9 4.0 3.3 4.9 4.1 s t es sector erase (8k) not preprogrammed preprogrammed 0.7 0.6 1.1 1.0 1.36 1.26 s t es bank 0 erase (256k) not preprogrammed preprogrammed 8.0 6.6 13.7 11.2 17.2 14.0 s t es bank 1 erase (16k) not preprogrammed preprogrammed 0.9 0.8 1.5 1.3 1.87 1.66 s t rpd recovery from power-down 20 s t psl program suspend latency 10 s t esl erase suspend latency 300 s symbol parameter conditions value unit min typ max endurance 10 kcycles endurance (bank1 sectors) 100 kcycles data retention 20 years t esr erase suspend rate min time from erase resume to next erase suspend 20 ms .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 38/49 2.10 external memory bus timing v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. the tables below use a variable which is derived from the emi_bconn registers (described in the str71x reference manual) and represents the special characteristics of the programmed memory cycle. table 21. emi read operation see figure 10 , figure 11 , figure 12 and figure 13 for related timing diagrams. table 22. emi write operation see figure 14 , figure 15 , figure 16 and figure 17 for related timing diagrams. symbol parameter value t mclk cpu clock period 1 / f mclk t c memory cycle time wait states t mclk x (1 + [c_length]) symbol parameter test conditions value unit min typ max t rcr read to csn removal time t mclk ns t rp read pulse time t c ns t rds read data setup time 3 ns t rdh read data hold time 3 ns t ras read address setup time 1.3*t mclk ns t rah read address hold time 3 ns t rat read address turnaround time 3 ns t rrt rdn turnaround time t mclk ns symbol parameter test conditions value unit min typ max t wcr wen to csn removal time t mclk ns t wp write pulse time t c ns t wds write data setup time 3 ns t wdh write data hold time 3 ns t was write address setup time 1.3*t mclk ns t wah write address hold time 3 ns t wat write address turnaround time 3 ns t wwt wen turnaround time t mclk ns .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 39/49 figure 10. read cycle timing: 16-bit read on 16-bit memory figure 11. read cycle timing: 32-bit read on 16-bit memory see table 21 for read timing data. csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah t rp csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 40/49 figure 12. read cycle timing: 16-bit read on 8-bit memory figure 13. read cycle timing: 32-bit read on 8-bit memory see table 21 for read timing data. csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp t rrt t rah address t rat t rp data input t rds t rdh t rrt t rah address t rat t rp data input t rds t rdh .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 41/49 figure 14. write cycle timing: 16-bit write on 16-bit memory figure 15. write cycle timing: 32-bit write on 16-bit memory see table 22 for write timing data. csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wdh t wcr t was t wds t wah t wp csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 42/49 figure 16. write cycle timing: 16-bit write on 8-bit memory figure 17. write cycle timing: 32-bit write on 8-bit memory see table 22 for write timing data. csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp t wwt t wah address t wat t wp data output t wds t wdh t wwt t wah address t wat t wp data output t wds t wdh .com .com .com .com .com 4 .com u datasheet
str71xf - electrical characteristics 43/49 2.11 adc electrical characteristics v 33 = 3.3 10%, av dd = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 23. adc electrical characteristics symbol parameter test conditions value unit min typ max res resolution sinewave with ? v in amplitude 12 bits ? v in input voltage range 0 2.5 v f mod modulator oversampling fre- quency 2.1 mhz ibw input bandwidth f mod / 4096 khz n ch number of input channels 4 n pbr passband ripple 0.1 db sinad s/n and distortion 56 63 db thd total harmonic distortion 60 74 db z in input impedance f mod = 2 mhz 1 m ? c in input capacitance 5 pf i adc power consumption t a = 27 c 2.5 3.0 ma i stby standby power consumption t a = 27 c 1 a .com .com .com .com .com 4 .com u datasheet
str71xf - package characteristics 44/49 3 package characteristics 3.1 package mechanical data figure 18. 64-pin thin quad flat package (10x10) figure 19. 144-pin thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 a a2 a1 c h l1 l e e1 d d1 e b dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 21.80 22.00 22.20 0.858 0.867 0.874 d1 19.80 20.00 20.20 0.780 0.787 0.795 d3 17.50 0.699 e 21.80 22.00 22.20 0.858 0.867 0.874 e1 19.80 20.00 20.20 0.780 0.787 0.795 e3 17.50 0.699 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 144 a a2 a1 b c 36 37 72 73 108 109 144 e1 e d1 d 1 h b l l1 seating plane 0.10mm .004 in. e e3 d3 .com .com .com .com .com 4 .com u datasheet
str71xf - package characteristics 45/49 figure 20. 64-low profile fine pitch ball grid array package figure 21. 144-low profile fine pitch ball grid array package dim. mm inches min typ max min typ max a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 7.750 8.000 8.150 0.305 0.315 0.321 d1 5.600 0.220 e 7.750 8.000 8.150 0.305 0.315 0.321 e1 5.600 0.220 e 0.720 0.800 0.880 0.028 0.031 0.035 f 1.050 1.200 1.350 0.041 0.047 0.053 ddd 0.120 0.005 number of pins n 64 dim. mm inches min typ max min typ max a 1.21 1.70 0.048 0.067 a1 0.21 0.008 a2 1.12 0.044 b 0.35 0.40 0.45 0.014 0.016 0.018 d 9.85 10.00 10.15 0.388 0.394 0.400 d1 8.80 0.346 e 9.85 10.00 10.15 0.388 0.394 0.400 e1 8.80 0.346 e 0.80 0.031 f 0.60 0.024 ddd 0.10 0.004 eee 0.15 0.006 fff 0.08 0.003 number of pins n 144 .com .com .com .com .com 4 .com u datasheet
str71xf - package characteristics 46/49 3.2 thermal characteristics the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja )(1) where: ?t a is the ambient temperature in c, ? ja is the package junction-to- ambient thermal resistance, in c/w, ?p d is the sum of p int and p i/o (p d = p int + p i/o ), ?p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. ?p i/o represents the power dissipation on input and output pins; most of the time for the applications p i/o < p int and may be neglected. on the other hand, p i/o may be significant if the device is configur ed to drive continuously external modules and/ or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: ? k is a constant for the particular part, which may be determined from equation (3) by meas- uring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a . table 24. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient tqfp 144 - 20 x 20 mm / 0.5 mm pitch 42 c/w ja thermal resistance junction-ambient tqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 c/w ja thermal resistance junction-ambient lfbga 64 - 8 x 8 x 1.7mm tbd c/w ja thermal resistance junction-ambient lfbga 144 - 10 x 10 x 1.7mm tbd c/w .com .com .com .com .com 4 .com u datasheet
str71xf - order codes 47/49 4 order codes table 25. order codes partnumber flash kbytes ram kbytes emi usb can i/o ports package temp. range STR710Fz1t6 128+16 32 yes yes yes 48 tqfp144 20 x 20 -40 to +85c STR710Fz2t6 256+16 64 STR710Fz1h6 128+16 32 yes yes yes 48 lfbga 10 x 10 1.7 STR710Fz2h6 256+16 64 str711fr0h6 64+16 16 no yes no 30 lfbga64 8 x 8 1.7 str711fr0t6 64+16 16 tqfp64 10x10 str711fr1t6 128+16 32 str711fr2t6 256+16 64 str712fr0h6 64+16 16 no yes 32 lfbga64 8 x 8 1.7 str712fr0t6 64+16 16 tqfp64 10 x10 str712fr1t6 128+16 32 str712fr2t6 256+16 64 str715fr0h6 64+16 16 no lfbga64 8 x 8 1.7 str715fr0t6 64+16 16 tqfp64 10 x 10 .com .com .com .com .com 4 .com u datasheet
str71xf - revision history 48/49 5 revision history table 26. revision history date revision description of changes 17-mar-2004 1 first release 05-apr-2004 2 updated ?electrical characteristics? on page 30 08-apr-2004 2.1 corrected str712f pinout. pins 43/42 swapped. 15-apr-2004 2.2 pdf hyperlinks corrected. 7-jul-2004 3 corrected description of stdby, v18, vss18 v18bkp vssbkp pins added iddrun typical data updated bspi ma x. baudrate. updated ?external memory bus timing? on page 38 29-oct-2004 4 corrected flash sector b1f0/f1 address in figure 6 on page 27 corrected table 6 on page 21 tqfp64 test pin is 16 instead of 17. added to tqpfp64 column: pin 7 booten, pin 17 v 33io-pll changed description of jtck from ?external pull-down required? to ?ex- ternal pull-up or pull down required?. 25-jan-2005 5 changed ?product preview? to ?preliminary data? on page 1 and 3 renamed ?pu/pd? column to ?reset state? in table 6 on page 21 added reference to str7 flash programming reference manual 19-apr-2005 6 added str715f devices and modified ram size of str71xf1 devices added bga package in section 3 updated ordering information in section 4 . added pll duty cycle min and max. in section 2.8 .com .com .com .com .com 4 .com u datasheet
str71xf - revision history 49/49 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com .com .com .com .com 4 .com u datasheet

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